Prof. Dr. Sergei Sawitzki

04103 - 80 48 - 37

Raum: 208

Sprechzeiten im Semester: Mo. 13:00-14:30 Uhr
Sprechzeiten in der vorlesungsfreien Zeit: nach Vereinbarung

Publikationen

Bücher und Buchbeiträge

  • Dielissen, J. T. M. H.; Engin, N.; Sawitzki, S.; van Berkel, C. H., Multi-Standard FEC Decoders for Wireless Devices: Scalability Issues and Multi-standard Capabilities, in Tasic, A.; Serdijn, W. A.; Larson, L. E.; Setti, G. (editors), Circuits and Systems for Future Generations of Wireless Communications, Series on Integrated Circuits and Systems, pp. 271-297, Springer, Berlin, 2009.
  • Kumar, A.; Sawitzki, S., High Throughput and Low Power Reed Solomon Decoder for Ultra Wide Band, in Verhaegh, W.; Aarts, E.; Korst, J. (editors), Intelligent Algorithms im Ambient and Biomedical Computing, Vol. 7 of Philips Research Book Series, pp. 299-316, Springer, Dordrecht, The Netherlands, 2006.
  • Sawitzki, S., Architektur und Entwurfsfluss zur Unterstützung der Anwendungsparallelität durch rekonfigurierbare Rechnersysteme, in Wagner, D.; u. a. (Hrsg.), Ausgezeichnete Informatikdissertationen 2002, Lecture Notes in Informatics, S. 143-152, Köllen Druck+Verlag GmbH, Bonn, 2003.
  • Sawitzki, S., Anwendungsparallelität und rekonfigurierbare Rechnersysteme: Entwurfsraum, Architekturvorlage, Entwurfsfluss, Mensch und Buch Verlag, Berlin, 2002, Gewerbliche Drucklegung der Dissertation.
  • Sawitzki, S.; Spallek, R. G., Kapitel 4: Computer, in Schneider, U.; Werner, D. (Hrsg.), Taschenbuch der Informatik, 3. Auflage, S. 87-122, Fachbuchverlag Leipzig im Carl Hanser Verlag, 2000, aktualisierte Version auch in der 4. Auflage (2001) enthalten.

Fachzeitschriften

  • Bostelmann, T.; Kewisch, P.; Bublies, L.; Sawitzki, S., Improving FPGA-Placement with a Self-Organizing Map Accelerated by GPU-Computing. International Journal On Advances in Systems and Measurements,  10(1 & 2):45-55, 2017.
  • Schulze, S.; Sawitzki, S.,  Processor Design Using a Functional Hardware Description Language. Microporcessors and Microsystems, 36(8):676-694, November 2012.
  • Habib, I.; Paker, Ö.; Sawitzki, S., Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation. IEEE Transactions on VLSI Systems, 18(5):794-807, May 2010.
  • Dielissen, J. T. M. H.; Engin, N.; Sawitzki, S.; van Berkel, C. H., Multi-Standard FEC Decoders for Wireless Devices. IEEE Transactions on Circuits and Systems II, 55(3):284-288, March 2008.

Patente

  • Tang, W.; Engin, N.; Steenhof, F. A.; Klaassen, M.; Hekstra, A. P.; Sawitzki, S., Multi-Standard Viterbi Processor, US Patent 8,904,266 B2, December 2, 2014, NXP B. V., Eindhoven, The Netherlands.
  • Pu, T.; Sawitzki, S., Deinterleaver for a Communication Device, US Patent 8,214,697 B2, July 3, 2012, NXP B. V., Eindhoven, The Netherlands.
  • Danilin, A. A.; Bennebroek, M. T.; Sawitzki, S., Configurable Logic Device, US Patent 8,076,955 B2, December 13, 2011, ST-Ericsson SA, Geneva, CH.
  • Danilin, A. A.; Bennebroek, M. T.; Sawitzki, S., Configurable Logic Device, US Patent 7,982,495 B2, July 19, 2011, ST-Ericsson SA, Geneva, CH.
  • Sawitzki, S.; van Berkel, C. H., Single Memory with Multiple Shift Register Functionality, US Patent 7,774,573 B2, August 10, 2010, ST-Ericsson SA, Geneva, CH.
  • Sawitzki, S.; van Berkel, C. H., Single Memory with Multiple Shift Register Functionality, European Patent EP 1,644,820 B1, May 21, 2008, NXP B. V., Eindhoven, The Netherlands.

Fachtagungsbeiträge

  • Starke, T. F.; Bostelmann, T.; Sawitzki, S., FPGA-basierter Protein- und DNA-Sequenzvergleich zur optimierten Datenbanksuche mit dem BLAST-Algorithmus, in Eibl, M.; Gaedke, M. (Hrsg.), Informatik 2017, Band 257 von Lecture Notes in Informatics (LNI), S. 469-480, Gesellschaft für Informatik, Bonn, Deutschland, 25.-29. September 2017, Chemnitz, Deutschland.
  • Bostelmann, T.; Starke, T. F.; Sawitzki, S., Local Alignment Search in Genetic Sequences on a Low-Cost FPGA, in Mady, A. E.-D.; Bostelmann, T.; Sawitzki, S. (editors), CENICS: The Tenth International Conference on Advances in Circuits, Electronics and Micro-Electronics, pp. 39-43, International Academy, Research, and Industry Association, Wilmington, DE, USA, September 10-14, 2017, Rome, Italy.
  • Starke, T. F.; Bostelmann, T.; Karafiat, H.; Sawitzki, S., A Synthesizable VHDL Export for the Custom Architecture Design Tool CustArD, in Mady, A. E.-D.; Bostelmann, T.; Sawitzki, S. (editors), CENICS: The Tenth International Conference on Advances in Circuits, Electronics and Micro-Electronics, pp. 44-48, International Academy, Research, and Industry Association, Wilmington, DE, USA, September 10-14, 2017, Rome, Italy.
  • Bostelmann, T.; Sawitzki, S., Improving the Performance of a SOM-based FPGA-Placement-Algorithm Using SIMD-Hardware, in Scholz, S. G.; Brunet, A.; Schranzhofer, L. (editors),  CENICS: The Ninth International Conference on Advances in Circuits, Electronics and Micro-Electronics, pp. 13-15, International Academy, Research, and Industry Association, Wilmington, DE, USA, July 24-28, 2016, Nice, France.
  • Sawitzki, S., Adaptive Architekturen für Vorwärtsfehlerkorrektur, in Vierhaus, H. T. (Hrsg.), DASS 2016 Tagungsband: Dresdner Arbeitstagung für Schaltungs- und Systementwurf, S. 37-40, Fraunhofer Verlag, Stuttgart, 10.-11. Mai 2016, Cottbus, Deutschland.
  • Bostelmann, T.; Sawitzki, S., Ein Entwurfsfluss für die geführte Optimierung rekonfigurierbarer Architekturen, in Vierhaus, H. T. (Hrsg.), DASS 2016 Tagungsband: Dresdner Arbeitstagung für Schaltungs- und Systementwurf, S. 47-50, Fraunhofer Verlag, Stuttgart, 10.-11. Mai 2016, Cottbus, Deutschland.
  • Bostelmann, T.; Sawitzki, S., Towards a Guided Design Flow for Heterogeneous Reconfigurable Architectures, in Cheung, P.; Luk, W.; Silvano, C. (editors), 25th International Conference on Field Programmable Logic and Applications, pp. 23-24, Imperial College, London, UK, September 2-4, 2015, London, UK.
  • Bostelmann, T.; Sawitzki, S., A Heterogeneous Architecture Template for Application Domain Specific Reconfigurable Logic, in Proceedings of the 23rd Austrian Workshop on Microelectronics, IEEE Computer Society Conference Publishing Services, Los Alamitos, CA, USA, 28 September 2015, Vienna, Austria.
  • Bostelmann, T.; Sawitzki, S., A Conceptual Toolchain for an Application Domain Specific Reconfigurable Logic Architecture, in Huebner, M.; Wirthlin, M.; Cumplido, R. (editors), 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig14), pp. 1-4, IEEE, Piscataway, NJ, USA, December 8-10, 2014, Cancun, Mexico.
  • Bostelmann, T.; Sawitzki, S., Improving FPGA Placement with a Self-Organizing Map, in Cumplido, R.; de la Torre, E.; Wirthlin, M. (editors), 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig13), pp. 1-6, IEEE, Piscataway, NJ, USA, December 9-11, 2013, Cancun, Mexico.
  • Bostelmann, T.; Sawitzki, S., Einsetzbarkeit selbstorganisierender Karten für die Platzierung von Netzlisten, in Schneider, P.; Klotz, T. (Hrsg.), DASS 2013 Tagungsband: Dresdner Arbeitstagung für Schaltungs- und Systementwurf, S. 56-61, Fraunhofer Verlag, Stuttgart, 25.-26. April 2013, Dresden, Deutschland.
  • Bostelmann, T.; Sawitzki, S., Automatische und teilautomatische Generierung anwendungsspezifischer Beschleunigungshardware aus der Softwarebeschreibung, in Elst, G.; Klotz, T. (Hrsg.), DASS 2011 Tagungsband: Dresdner Arbeitstagung für Schaltungs- und Systementwurf, S. 108-113, Fraunhofer Verlag, Stuttgart, 3.-4. Mai 2011, Dresden, Deutschland.
  • Schulze, S.; Sawitzki, S., Entwurf und Implementierung eines adaptiven Prozessors in einer funktionalen Hardwarebeschreibungssprache, in Elst, G.; Klotz, T. (editors), DASS 2011 Tagungsband: Dresdner Arbeitstagung für Schaltungs- und Systementwurf, S. 90-95, Fraunhofer Verlag, Stuttgart, 3.-4. Mai 2011, Dresden.
  • Schulze, S.; Sawitzki, S., Design, Implementation and Verification of an Adaptable Processor in Lava HDL, in Koch, A.; Krishnamurthy, R.; McAllister, J.; Woods, R.; El-Ghazawi, T. (editors), Reconfigurable Computing: Architectures, Tools and Applications. 7th International Symposium, ARC 2011 Proceedings, Vol. 6578 of Lecture Notes in Computer Science, pp. 145-156, Springer, Heidelberg, March 23-25, 2011, Belfast, UK.
  • Danilin, A. A.; Sawitzki, S.; Rijshouwer, E. J. C., Reconfigurable Cell Architecture for Multi-Standard Interleaving and Deinterleaving in Digital Communication Systems, in Kebschull, U.; Platzner, M.; Teich, J. (editors), 2008 International Conference on Field-Programmable Logic and Applications, pp. 527-530, IEEE, Piscataway, NJ, USA, September 8-10, 2008, Heidelberg, Germany.
  • Danilin, A. A.; Bennebroek, M. T.; Sawitzki, S., A Novel Routing Architecture for Field-programmable Gate-arrays, in Brinkschulte, U.; Ungerer, T.; Hochberger, C.; Spallek, R. G. (editors), Proceedings of the 21st International Conference on Architecture of Computing Systems, ARCS'08, pp. 144-158, Springer-Verlag, Berlin, Heidelberg, 25-28 February 2008, Dresden, Germany.
  • Nelissen, M.; van Berkel, C. H.; Sawitzki, S., Mapping VLIWxSIMD Processor on an FPGA: Scalability and Performance, in Bertels, K.; Najjar, W. A.; van Genderen, A. J.; Vassiliadis, S. (editors), FPL 2007, International Conference on Field-Programmable Logic and Applications, pp. 521-524, IEEE, Piscataway, NJ, USA, August 27-29, 2007, Amsterdam, The Netherlands.
  • Danilin, A. A.; Sawitzki, S., A Novel Reconfigurable Architecture for Temporal and Spatial Application Mapping, in Boemo, E.; de Castro, A.; Sutter, G.; Todorovich, E. (editors), Proceeding of 2007 3rd International Conference on Programmable Logic, pp. 69-74, IEEE, Piscataway, NJ, USA, 26-28 February 2007, Mar del Plata, Argentina.
  • Krishnaiah, G.; Engin, N.; Sawitzki, S., Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets, in Design, Automation and Test in Europe Conference and Exhibition, DATE 2007, pp. 1563-1568, European Design and Automation Association, Leuven, Belgium, April 16-20, 2007, Nice, France.
  • Danilin, A. A.; Bennebroek, M. T.; Sawitzki, S., ASTRA: An Advanced Space-Time Reconfigurable Architecture, in Koch, A.; Leong, P.; Boemo, E. (editors), Proceeding of 2006 International Conference on Field-Programmable Logic and Applications, pp. 773-776, IEEE, Piscataway, NJ, USA, August 28-30, 2006, Madrid, Spain.
  • Kumar, A.; Sawitzki, S., High Throughput Reed-Solomon Decoder for Ultra Wide Band, in Proceedings of the Philips Digital Signal Processing Conference, Philips B. V., Amsterdam, The Netherlands, 15-16 November 2005, Veldhoven, The Netherlands.
  • Kumar, A.; Sawitzki, S., High-Throughput and Low-Power Architectures for Reed Solomon Decoder, in Matthews, M. B. (editor), Conference Record of the Thirty-Ninth Asilomar Conference on Signals, Systems & Computers, pp. 990-994, IEEE, Piscataway, NJ, USA, October 29-November 1, 2005, Pacific Grove, CA, USA.
  • Danilin, A. A.; Bennebroek, M. T.; Sawitzki, S., A Novel Toolset for the Development of FPGA-like Reconfigurable Logic, in Rissa, T.; Wilton, S.; Leong, P. (editors), Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), pp. 640-643, IEEE, Piscataway, NJ, USA, August 24-26, 2005, Tampere, Finland.
  • Danilin, A. A.; Sawitzki, S., Optimizing the Performance of the Simulated Annealing Based Placemement Algorithms for Island-Style FPGAs, in Becker, J.; Platzner, M.; Vernalde, S. (editors), Field-Programmable Logic and Applications. 14th International Conference, FPL 2004, Vol. 3203 Lecture Notes in Computer Science, pp. 852-856, Springer-Verlag, Berlin, Heidelberg, August 30-September 1, 2004, Antwerp, Belgium.
  • Sawitzki, S.; Spallek, R. G., Werkzeuge zur Synthese und Optimierung rekonfigurierbarer Rechnerysteme, in Schüffny, R.; Hansen, C.; Elst, G. (editors), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'2004), Intellectual Property Principien Workshop, S. 118-123, Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 19.-20. April 2004, Dresden.
  • Padiy, A.; Modrie, D.; Sawitzki, S., Fast Parallel Viterbi Bit Detection for Optical Storage Systems, in Proceedings of the 3rd Philips Conference on Digital Signal Processing, Koninklijke Philips Electronics N.V., Eindhoven, The Netherlands, 11-12 November 2003, Veldhoven, The Netherlands
  • Sawitzki, S.; Spallek, R. G., Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms, in Cheung, P. Y. K.; Constantinides, G. A.; de Sousa, J. T. (editors), Field-Programmable Logic and Applications. 13th International Conference, FPL 2003, Vol. 2778 of Lecture Notes in Computer Science, pp. 1119-1122, Springer-Verlag, Berlin, Heidelberg, September 1-3, 2003, Lisbon, Portugal.
  • Sawitzki, S.; Spallek, R. G., ReSArT: Eine Skalierbare Architekturvorlage für die Synthese rekonfigurierbarer Rechnerysteme, in Elst, G.; Schüffny, R.; Fettweis, G.~P. (Hrsg.), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'2003) und Workshop System Design Automation (SDA'2003), S. 111-116, Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 8.-9. Mai 2003, Dresden.
  • Hatnik, U.; Sawitzki, S.; Spallek, R. G., Entwurfsunterstützung von heterogenen Kommunikationssystemen durch verteilte objektorientierte Simulation, in Tavangarian, D. (Hrsg.), Simulationstechnik - ASIM 2002: 16. Symposium, Band 12 von ASIM-Fortschritte in der Simulationstechnk, SCS-Europe BVBA, 10.-13. September 2002, Rostock.
  • Hatnik, U.; Sawitzki, S., Distributed Object-Oriented Simulation of Heterogeneous Communication Systems, in Ubertini, L. (editor), Proceedings of the IASTED International Conference on Applied Simulation and Modelling, pp. 283-288, Acta Press, Calgary, Canada, 25-28 June 2002, Crete, Greece.
  • Köhler, S.; Braunes, J.; Sawitzki, S.; Spallek, R. G., Improving Code Efficiency for Reconfigurable VLIW Processors, in Proceedings International Parallel and Distributed Processing Symposium: IPDPS 2002 Workshops, p. 153-159, IEEE, Piscataway, NJ, USA, 15-19 April 2002, Fort Lauderdale, FL, USA.
  • Hatnik, U.; Sawitzki, S.; Spallek, R. G., Verteilte objektorientierte Simulation heterogener Kommunikationssysteme, in Schüffny, R.; Elst, G. (Hrsg.), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'2002), S. 95-100, Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 21.-22. März 2002, Dresden.
  • Braunes, J.; Köhler, S.; Sawitzki, S.; Spallek, R. G., Reconfigurable Architectures and Compilations Techniques for Explotation of Application Parallelism, in Jähnichen, S.; Zhou, X. (editors), Proceedings of the Fourth International Workshop on Advanced Parallel Processing Technologies, pp. 242-247, September 17-19, 2001, Ilmenau.
  • Sawitzki, S.; Köhler, S.; Spallek, R. G., Prototyping Framework for Reconfigurable Processors, in Brebner, G.; Woods, R. (editors), Proceedings of the 11th International Conference on Field-Programmable Logic and Applications, Vol. 2147 of Lecture Notes in Computer Science, pp. 6-15, Springer-Verlag, Berlin, Heidelberg, 27-29 August 2001, Belfast, Northern Ireland, UK.
  • Dielissen, J. T. M. H.; van Meerbergen, J. L.; Bekooij, M.; Harmsze, F.; Sawitzki, S.; Huisken, J.; van der Werf, A., Power Efficient Layered Turbo Decoder Implementation, in Nebel, W.; Jerraya, A. (editors), Proceedings Design, Automation and Test in Europe Conference and Exhibition 2001, pp. 246-251, IEEE, Piscataway, NJ, USA, March 13-16, 2001, Munich, Germany.
  • Sawitzki, S.; Köhler, S.; Spallek, R. G., Reconfigurability in Embedded Microprocessors: A Prototyping Study, in Schlag, M.; Tessier, R. (editors), Proceedings of the 2001 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, p. 228, ACM, New York, NY, USA, February 11-13, 2001, Monterey, CA, USA.
  • Bekooij, M.; Dielissen, J. T. M. H.; Harmsze, F.; Sawitzki, S.; van der Werf, A.; van Meerbergen, J. L., Power-Efficient Application-Specific VLIW Processor for Turbo Decoding, in Wuorinen, J. H. (editor), 2001 IEEE International Solid-State Circuits Conference. Digest of Tehcnical Papers, pp. 180-181, IEEE, Piscataway, NJ, USA, February 2001, San Francisco, CA, USA.
  • Sawitzki, S.; Spallek, R. G.; Schönherr, J.; Straube, B., Formal Verification of a Reconfigurable Microprocessor, in Hartenstein, R. W.; Grünbacher, H. (editors), Field-Programmable Logic and Applications: the Roadmap to Reconfigurable Computing, Vol. 1896 of Lecture Notes in Computer Science, pp. 781-784, Springer-Verlag, Berlin, Heidelberg, August 27-30, 2000, Villach, Austria.
  • Köhler, S.; Sawitzki, S.; Spallek, R. G., Digital Signal Processors for Multimedia Applications, in Proceedings of the 4th World Multiconference on Systemics, Cybernetics and Informatics and the 6th International Conference on Information Systems, Analysis and Synthesis (SCI/ISAS 2000), Volume VI, Image Acoustic, Speech and Signal Processing: Part II, pp. 106-112, International Institute of Informatics and Systemics, Winter Garden, FL, USA, 23-26 June 2000, Orlando, FL, USA.
  • Sawitzki, S.; Spallek, R. G.; Schönherr, J.; Straube, B., Formal Verification for Microprocessors with Extendable Instruction Set, in Swartzlander, Jr., E. E.; Jullien, G. A.; Schulte, M. J. (editors), Proceedings IEEE International Conference on Application-specific Systems, Architectures, and Processors, pp. 47-55, IEEE, Piscataway, NJ, USA, July 10-12, 2000, Boston, MA, USA.
  • Köhler, S.; Sawitzki, S.; Spallek, R. G., Digitale Signalverarbeitung mit dynamisch rekonfigurierbaren Architekturen, in Schüffny, R.; Elst, G. (Hrsg.), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'2000), Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 16.-17. Mai 2000, Dresden.
  • Sawitzki, S.; Köhler, S.; Spallek, R. G., Prototyping-Umgebung für rekonfigurierbare Mikroprozessoren auf FPGA-Basis, in Schüffny, R.; Elst, G. (Hrsg.), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'2000), Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 16.-17. Mai 2000, Dresden.
  • Sawitzki, S.; Köher, S.; Spallek, R. G.; Schneider, J.; Rülke, S., Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe, in Grimm, C.; Waldschmidt, K. (Hrsg.), Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, S. 236-244, VDE Verlag, Berlin, 28. Februar-1. März 2000, Frankfurt.
  • Sawitzki, S.; Köher, S.; Spallek, R. G.; Schneider, J.; Rülke, S., Quantitative Comparison of Different Design Approaches for FPGA-based Design Flows, in Proceedings of the International Workshop on IP Based Synthesis and System Design, pp. 241-245, Institut National Polytechnique de Grenoble, Grenoble, France, December 14-15, 1999, Grenoble, France.
  • Sawitzki, S., Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme, in Beiersdörfer, K.; Engels, G.; Schäfer, W. (Hrsg.), Informatik'99 - Informatik überwindet Grenzen. 29. Jahrestagung der Gesellschaft für Informatik, S. 239-246, Springer-Verlag, Berlin, Heidelberg, 5.-9. Oktober 1999, Paderborn.
  • Sawitzki, S.; Spallek, R. G., A Concept for an Evaluation Framework for Reconfigurable Systems, in Lysaght, P.; Irvine, J.; Hartenstein, R. W. (editors), Field-Programmable Logic and Applications: 9th International Workshop, Vol. 1673 of Lecture Notes in Computer Science, pp. 475-480, Springer-Verlag, Berlin, Heidelberg, August 30-September 1, 1999, Glasgow, UK.
  • Sawitzki, S.; Spallek, R. G., Klassifikation und Leistungsbewertung rekonfigurierbarer Rechnersysteme, in Schüffny, R.; Elst, G. (Hrsg.), Dresdner Arbeitstagung Schaltkreis- und Systementwurf (DASS'99), Fraunhofer-Institut für Integrierte Schaltungen, Dresden, 19.-20. Mai 1999, Dresden.
  • Köhler, S.; Sawitzki, S.; Gratz, A.; Spallek, R. G., Digital Signal Processing with General Purpose Microprocessors, DSP and Reconfigurable Logic, in Rolim, J.; Mueller, F.; Zomaya, A. Y.; Ercal, F.; Olariu, S.; Ravindran, B.; Gustafsson, J.; Takada, H.; Olsson, R.; Kale, L. V.; Beckman, P.; Haines, M.; ElGindy, H.; Caromel, D.; Chaumette, S.; Fox, G.; Pan, Y.; Li, K.; Yang, T.; et al. (editors), Parallel and Distributed Processing. 11 IPPD/SPDP Workshops held in Conjunction with the 13th International Parallel Processing Symposium and the 10th Symposium on Parallel and Distributed Processing, Vol. 1586 of Lecture Notes in Computer Science, pp. 706-708, Springer-Verlag, Berlin, Heidelberg, April 12-16, 1999, San Juan, Puerto Rico.
  • Köhler, S.; Sawitzki, S.; Gratz, A.; Spallek, R. G., Digital Signal Processing: A Performance Comparison, in Bagherzadeh, N. (editor), Proceedings of the International Conference on Parallel Architectures and Compilation Techniques. Workshop on Reconfigurable Computing, pp. 113-116, October 1998, Paris, France.
  • Sawitzki, S.; Gratz, A.; Spallek, R. G., CoMPARE: A Simple Reconfigurable Processor Architecture Exploiting Instruction Level Parallelism, in Hawick, K. A.; James, H. A. (editors), Proceedings of the 5th Australasian Conference on Parallel and Real-Time Systems, pp. 213-224, Springer-Verlag, Singapore, Berlin, 28-29 September 1998, Adelaide, Australia.
  • Sawitzki, S.; Gratz, A.; Spallek, R. G., Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays, in Hartenstein, R. W.; Keevallik, A. (editors), Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm. Proceedings of the 8th International Workshop, Vol. 1482 of Lecture Notes in Computer Science, pp. 411-415, Springer-Verlag, Berlin, Heidelberg, August 31-September 3, 1998, Tallinn, Estonia.